\doxysection{UART\+\_\+\+Init\+Type\+Def Struct Reference}
\hypertarget{struct_u_a_r_t___init_type_def}{}\label{struct_u_a_r_t___init_type_def}\index{UART\_InitTypeDef@{UART\_InitTypeDef}}


UART Init Structure definition.  




{\ttfamily \#include $<$stm32h7xx\+\_\+hal\+\_\+uart.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_u_a_r_t___init_type_def_ae460c2e4d7ddc67bca9f5756f45b1d83}{Baud\+Rate}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_u_a_r_t___init_type_def_a0f1cd85e62aa4fd4b36ee9e610e7789f}{Word\+Length}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_u_a_r_t___init_type_def_a6717dfe595617c7b2d57139d9cd306ef}{Stop\+Bits}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_u_a_r_t___init_type_def_adc92243425cb18cb8b5f03692841db48}{Parity}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_u_a_r_t___init_type_def_ab2ee6ea5a5d4ca5ee6b759be197bcfcb}{Mode}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_u_a_r_t___init_type_def_adbf4734130666b94201c6658464c1622}{Hw\+Flow\+Ctl}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_u_a_r_t___init_type_def_a77c2c86a2186e09cbf022e27c0c82324}{Over\+Sampling}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_u_a_r_t___init_type_def_a1662b82dc43d9137c3a4485794c94388}{One\+Bit\+Sampling}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_u_a_r_t___init_type_def_af611d87f44dd63f0719f202f92c90df3}{Clock\+Prescaler}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
UART Init Structure definition. 

\label{doc-variable-members}
\Hypertarget{struct_u_a_r_t___init_type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_u_a_r_t___init_type_def_ae460c2e4d7ddc67bca9f5756f45b1d83}\index{UART\_InitTypeDef@{UART\_InitTypeDef}!BaudRate@{BaudRate}}
\index{BaudRate@{BaudRate}!UART\_InitTypeDef@{UART\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{BaudRate}{BaudRate}}
{\footnotesize\ttfamily \label{struct_u_a_r_t___init_type_def_ae460c2e4d7ddc67bca9f5756f45b1d83} 
uint32\+\_\+t UART\+\_\+\+Init\+Type\+Def\+::\+Baud\+Rate}

This member configures the UART communication baud rate. The baud rate register is computed using the following formula\+: \hypertarget{struct_u_a_r_t___init_type_def_autotoc_md27}{}\doxysubsection{\texorpdfstring{LPUART\+:}{LPUART\+:}}\label{struct_u_a_r_t___init_type_def_autotoc_md27}
Baud Rate Register = ((256 \texorpdfstring{$\ast$}{*} lpuart\+\_\+ker\+\_\+ckpres) / ((huart-\/\texorpdfstring{$>$}{>}Init.\+Baud\+Rate))) where lpuart\+\_\+ker\+\_\+ck\+\_\+pres is the UART input clock divided by a prescaler \hypertarget{struct_u_a_r_t___init_type_def_autotoc_md28}{}\doxysubsection{\texorpdfstring{UART\+:}{UART\+:}}\label{struct_u_a_r_t___init_type_def_autotoc_md28}

\begin{DoxyItemize}
\item If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart\+\_\+ker\+\_\+ckpres) / ((huart-\/\texorpdfstring{$>$}{>}Init.\+Baud\+Rate)))
\item If oversampling is 8, Baud Rate Register\mbox{[}15\+:4\mbox{]} = ((2 \texorpdfstring{$\ast$}{*} uart\+\_\+ker\+\_\+ckpres) / ((huart-\/\texorpdfstring{$>$}{>}Init.\+Baud\+Rate)))\mbox{[}15\+:4\mbox{]} Baud Rate Register\mbox{[}3\mbox{]} = 0 Baud Rate Register\mbox{[}2\+:0\mbox{]} = (((2 \texorpdfstring{$\ast$}{*} uart\+\_\+ker\+\_\+ckpres) / ((huart-\/\texorpdfstring{$>$}{>}Init.\+Baud\+Rate)))\mbox{[}3\+:0\mbox{]}) \texorpdfstring{$>$}{>}\texorpdfstring{$>$}{>} 1 where uart\+\_\+ker\+\_\+ck\+\_\+pres is the UART input clock divided by a prescaler 
\end{DoxyItemize}\Hypertarget{struct_u_a_r_t___init_type_def_af611d87f44dd63f0719f202f92c90df3}\index{UART\_InitTypeDef@{UART\_InitTypeDef}!ClockPrescaler@{ClockPrescaler}}
\index{ClockPrescaler@{ClockPrescaler}!UART\_InitTypeDef@{UART\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{ClockPrescaler}{ClockPrescaler}}
{\footnotesize\ttfamily \label{struct_u_a_r_t___init_type_def_af611d87f44dd63f0719f202f92c90df3} 
uint32\+\_\+t UART\+\_\+\+Init\+Type\+Def\+::\+Clock\+Prescaler}

Specifies the prescaler value used to divide the UART clock source. This parameter can be a value of \doxylink{group___u_a_r_t___clock_prescaler}{UART Clock Prescaler}. \Hypertarget{struct_u_a_r_t___init_type_def_adbf4734130666b94201c6658464c1622}\index{UART\_InitTypeDef@{UART\_InitTypeDef}!HwFlowCtl@{HwFlowCtl}}
\index{HwFlowCtl@{HwFlowCtl}!UART\_InitTypeDef@{UART\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{HwFlowCtl}{HwFlowCtl}}
{\footnotesize\ttfamily \label{struct_u_a_r_t___init_type_def_adbf4734130666b94201c6658464c1622} 
uint32\+\_\+t UART\+\_\+\+Init\+Type\+Def\+::\+Hw\+Flow\+Ctl}

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of \doxylink{group___u_a_r_t___hardware___flow___control}{UART Hardware Flow Control}. \Hypertarget{struct_u_a_r_t___init_type_def_ab2ee6ea5a5d4ca5ee6b759be197bcfcb}\index{UART\_InitTypeDef@{UART\_InitTypeDef}!Mode@{Mode}}
\index{Mode@{Mode}!UART\_InitTypeDef@{UART\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{Mode}{Mode}}
{\footnotesize\ttfamily \label{struct_u_a_r_t___init_type_def_ab2ee6ea5a5d4ca5ee6b759be197bcfcb} 
uint32\+\_\+t UART\+\_\+\+Init\+Type\+Def\+::\+Mode}

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of \doxylink{group___u_a_r_t___mode}{UART Transfer Mode}. \Hypertarget{struct_u_a_r_t___init_type_def_a1662b82dc43d9137c3a4485794c94388}\index{UART\_InitTypeDef@{UART\_InitTypeDef}!OneBitSampling@{OneBitSampling}}
\index{OneBitSampling@{OneBitSampling}!UART\_InitTypeDef@{UART\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{OneBitSampling}{OneBitSampling}}
{\footnotesize\ttfamily \label{struct_u_a_r_t___init_type_def_a1662b82dc43d9137c3a4485794c94388} 
uint32\+\_\+t UART\+\_\+\+Init\+Type\+Def\+::\+One\+Bit\+Sampling}

Specifies whether a single sample or three samples\textquotesingle{} majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock deviations. This parameter can be a value of \doxylink{group___u_a_r_t___one_bit___sampling}{UART One Bit Sampling Method}. \Hypertarget{struct_u_a_r_t___init_type_def_a77c2c86a2186e09cbf022e27c0c82324}\index{UART\_InitTypeDef@{UART\_InitTypeDef}!OverSampling@{OverSampling}}
\index{OverSampling@{OverSampling}!UART\_InitTypeDef@{UART\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{OverSampling}{OverSampling}}
{\footnotesize\ttfamily \label{struct_u_a_r_t___init_type_def_a77c2c86a2186e09cbf022e27c0c82324} 
uint32\+\_\+t UART\+\_\+\+Init\+Type\+Def\+::\+Over\+Sampling}

Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f\+\_\+\+PCLK/8). This parameter can be a value of \doxylink{group___u_a_r_t___over___sampling}{UART Over Sampling}. \Hypertarget{struct_u_a_r_t___init_type_def_adc92243425cb18cb8b5f03692841db48}\index{UART\_InitTypeDef@{UART\_InitTypeDef}!Parity@{Parity}}
\index{Parity@{Parity}!UART\_InitTypeDef@{UART\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{Parity}{Parity}}
{\footnotesize\ttfamily \label{struct_u_a_r_t___init_type_def_adc92243425cb18cb8b5f03692841db48} 
uint32\+\_\+t UART\+\_\+\+Init\+Type\+Def\+::\+Parity}

Specifies the parity mode. This parameter can be a value of \doxylink{group___u_a_r_t___parity}{UART Parity} \begin{DoxyNote}{Note}
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits). 
\end{DoxyNote}
\Hypertarget{struct_u_a_r_t___init_type_def_a6717dfe595617c7b2d57139d9cd306ef}\index{UART\_InitTypeDef@{UART\_InitTypeDef}!StopBits@{StopBits}}
\index{StopBits@{StopBits}!UART\_InitTypeDef@{UART\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{StopBits}{StopBits}}
{\footnotesize\ttfamily \label{struct_u_a_r_t___init_type_def_a6717dfe595617c7b2d57139d9cd306ef} 
uint32\+\_\+t UART\+\_\+\+Init\+Type\+Def\+::\+Stop\+Bits}

Specifies the number of stop bits transmitted. This parameter can be a value of \doxylink{group___u_a_r_t___stop___bits}{UART Number of Stop Bits}. \Hypertarget{struct_u_a_r_t___init_type_def_a0f1cd85e62aa4fd4b36ee9e610e7789f}\index{UART\_InitTypeDef@{UART\_InitTypeDef}!WordLength@{WordLength}}
\index{WordLength@{WordLength}!UART\_InitTypeDef@{UART\_InitTypeDef}}
\doxysubsubsection{\texorpdfstring{WordLength}{WordLength}}
{\footnotesize\ttfamily \label{struct_u_a_r_t___init_type_def_a0f1cd85e62aa4fd4b36ee9e610e7789f} 
uint32\+\_\+t UART\+\_\+\+Init\+Type\+Def\+::\+Word\+Length}

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of \doxylink{group___u_a_r_t_ex___word___length}{UARTEx Word Length}. 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Inc/\mbox{\hyperlink{stm32h7xx__hal__uart_8h}{stm32h7xx\+\_\+hal\+\_\+uart.\+h}}\end{DoxyCompactItemize}
